1. Field of the Invention
The present invention relates to a parallel precoder circuit that processes parallel input information series, and outputs parallel output information series, and more particularly, to a parallel precoder circuit that is applied to a differential quadrature phase shift keying (DQPSK) system.
2. Description of the Related Art
In the optical communication system, an optical duobinary modulation system and a differential phase shift keying (DPSK) system are investigated as a technique of increasing a relay distance and increasing a transmission speed. On the other hand, in recent years, a multiple-value technique using a differential quadrature phase shift keying (DQPSK) system calls attention.
Circuits of a transmission and reception system of the optical communication system using the DQPSK system have a precoder, an encoder, and a decoder. The precoder performs differential encoding operations of an input set of 2-bit information series including an in-phase component signal and a quadrature-phase component signal, and one-bit delay feedback information series obtained by delaying the own output information series by one bit, and outputs the operated result. The encoder executes a base band modulation to information series as the output of the precoder, thereby obtaining and outputting a DQPSK signal. The decoder modulates the DQPSK signal output from the encoder, and demodulates the signal, thereby restoring the input set of the information series input to the precoder.
In the optical communication system, a distributed feedback (DFB) laser and a Mac-Zehnder modulator achieve the function of the encoder, and a photodetector achieves the function of the decoder in many cases. In other words, individual optical elements achieve the functions of the encoder and the decoder in many cases. On the other hand, a logical circuit is usually used for the precoder.
A transmission speed F [Hz] in the optical communication is an ultra-high speed of 10 Gb/s and 40 Gb/s. Therefore, when a serial precoder circuit that processes a signal as serial data according to the transmission speed F is used, the logical circuit is required to operate at an ultra-high speed.
When the transmission speed F becomes an ultra-high speed, a clock unit time per one bit becomes short. Therefore, timing adjustment of a circuit that achieves a one-bit delay becomes difficult.
To solve this problem, various techniques are conventionally considered. For example, a technique concerning a serial precoder circuit that operates at a high speed without structuring a feedback route within a DQPSK precoder by using a toggle flip-flop (T-FF) circuit is disclosed in M. Serbay, C. Wree and W. Rosenkranz, “Implementation of differential precoder for high-speed optical DQPSK transmission,” Electric Lett., vol. 40, no. 20, Sep. 2004.
The serial precoder circuit described in the above literature achieves the serial precoder circuit without structuring a feedback route within a DQPSK precoder. Therefore, a circuit that delays one bit is not necessary. Consequently, the difficulty of adjusting the timing of a circuit that achieves a one-bit delay cannot be avoided.
However, the serial precoder circuit described in the above literature does not solve strict requirement for the operation speed of logical circuits such as the T-FF circuit, a delay flip-flop circuit (D-FF) circuit, an inverting circuit, and AND circuit, an OR circuit, and an exclusive OR (EXOR) circuit. Therefore, it is difficult to achieve the serial precoder circuit according to the conventional technique described in the Nonpatent literature 1 by using a general-purpose application specific integrated circuit (ASIC), such as a framer, and a field-programmable gate array (FPGA).
In general, the requirement for the operation speed of the logical circuit can be lowered by achieving the function of the precoder, by serial-parallel converting the input information series, and processing the data with a parallel precoder circuit having plural serial precoders developed in parallel.
For example, in the case of the parallel precoder circuit that has a serial precoder circuit simply developed to x (2≦x, where x is a positive integer) parallel precoders, parallel input signal of information series (a set of an in-phase component signal and a quadrature-phase component signal) transmitted in advance in the serial transfer, that is, a parallel input signal that is old in time series, is input to the serial precoder circuit. Output information series obtained from the serial precoder circuit are connected in cascade as a one-bit delayed feedback signal of the serial precoder circuit that processes the output information series adjacent in the parallel signals. In this configuration, a feedback route that passes through x serial precoder circuits is generated. Therefore, even when the serial precoder circuit is developed in parallel, the operation speed required for the serial precoder circuit cannot be mitigated.
Assume that a circuit is configured to directly generate a parallel output signal from a parallel input signal, without using the output information series of the serial precoder circuit to which a parallel input signal old in time series is input as a one-bit delayed feedback signal of the last information series. In this case, a delay in the feedback route can be decreased. However, a scale of the circuits increases enormously.